NVIDIA Details Next-Gen Tegra Parker SOC at Hot Chips

NVIDIA has unveiled the very first architectural details for their adjacent-generation Tegra Parker SOC at Hot Chips. The latest Tegra SOC is based on TSMC's advanced FinFET process, combining the Pascal GPU and Denver 2 CPU compages for unprecedented increase in performance and efficiency. NVIDIA revealed at Hot Chips that they are currently focusing the SOC at automotive markets but there are possibilities that information technology could arrive in different solutions too.

NVIDIA Tegra Parker SOC Detailed - TSMC FinFET Process, Pascal GPU and Denver ii CPU Architecture

Starting with the details, the Tegra Parker SOC is based on the 16nm FinFET process node from TSMC and uses NVIDIA's latest CPU and GPU compages. The bulk of the mass is dedicated to the Pascal GPU cores and their Denver ii CPU cores. The chip features 256 CUDA cores that are based on the same DNA that is featured on the Titan X (Pascal) graphics card. The ARM v8 CPU complex comprises of ii Denver ii and 4 A57 cores with an coherent HMP (Heterogeneous Multi-Processor Architecture).

The Denver two and A57 fries each pack 2 MB of L2 cache and are linked via the HMP compages to evangelize 4 MB L2 cache. The Denver two chips also pack 128K+64K sub cache while the A57 chips include a 48K+32K sub-cache organization. In addition to the CPU cores, the unit of measurement too packs 128b LPDDR4 support with 50 GB/s bandwidth (ECC). Display is a triple pipeline (4K @ 60 FPS) link while camera features include machine-HDR technology on up to 12 cameras.

NVIDIA mentions that their Denver 2 chips are the most avant-garde and highest performance ARM CPUs with pregnant functioning improvements over first gen Denver cores. The new cores feature dynamic code optimizations, a vii-wide superscalar compages and several depression power retention states. This leads to a 40% performance increment in CPU performance over Apple tree's A9X scrap.

While NVIDIA may not reveal the full purpose of Tegra Parker aside from automotive, I believe they have hinted that Parker is as good as an gaming chip as it'south an automotive processor. The Multiprocessor architecture that combines big+super cores are mentioned to be great for single threaded performance, maximize the aggregate functioning and accept a sufficient thread count for automotive and gaming applications.

NVIDIA Tegra Parker SOC Supports Hardware Enabled Virtualization

The Tegra Parker SOC is also the showtime Tegra chip to back up Hardware enabled CPU, GPU and SOC Virtualization. The chip can drive up to 8 virtualized machines with each VM having its dedicated brandish pipeline. NVIDIA will also provide their own software solutions to deliver the best virtualization experience using the Tegra SOC.

The Tegra SOC besides supports 4K sixty FPS Encode/Decode, Ethernet-AVB, Dual Tin, QSPI for automotive, eMMC five.2 and SATA for storage, PCI-East and a dedicated sound-processing chip.

The Tegra Parker SOC is first featured on the Drive PX 2 which comes with two such Tegra modules and even more space to support dedicated MXM graphics cards. This production packs 12 CPU Cores, four Pascal GPUs (2 Tegra / 2 MXM) with 8 TFLOPs of FP32 and 24 TFLOPs of INT8 compute. Nosotros have already seen the production packing 2 GP106 GPUs in MXM form gene then we wait something close to the GTX 1060 (Notebook) on NVIDIA's Drive PX ii solution.

NVIDIA Drive PX Generation Comparison:

Product Proper name	NVIDIA Bulldoze PX	NVIDIA Drive PX two	NVIDIA Drive Xavier	NVIDIA Drive Pegasus	NVIDIA Drive AGX Orin
SOC Name	Tegra X1	Parker	Xavier	Xavier	Orin
Process Engineering science	20nm SOC	16nm FinFET	12nm FinFET	12nm FinFET	TBA
SOC Transistors	2 Billion (Tegra X1)	North/A	7 Billion (Xavier)	7 Billion (Xavier)	17 Billion (Orin)
GPU Architecture	Maxwell (256 Core)	Pascal (256 Cadre)	Volta (512 Core)	Volta (512 Core)	Ampere?
CPU	16 Core ARM CPU	12 Core ARM CPU	8 Cadre ARM CPU	16 Core ARM CPU	12 Cadre ARM CPU
CPU Architecture	8x Cortex A57 8x Cortex A53	4x Denver 8x Cortex A57	Carmel ARM64 8 Core CPU (eight MB L2 + four MB L3)	Carmel ARM64 8 Core CPU (8 MB L2 + 4 MB L3)	ARM Herclues Cores
Compute DLTOPs	N/A	xx DLTOPs	30 TOPs	320 TOPs	200 TOPs
Total Chips	two x Tegra X1	2 x Tegra X2 2 x Pascal MXM GPUs	ane ten Xavier	2 ten Volta 2 x Turing	i x Ampere
System Memory	LPDDR4	8 GB LPDDR4 (50+ GB/south)	sixteen GB 256-bit LPDDR4	LPDDR4 + GDDR6	N/A
Graphics Memory	Northward/A	4 GB GDDR5 (80+ GB/s)	137 GB/south	one TB/south	200 GB/s
TDP	20W	80W	30W	500W	TBA